1. Field of the Invention
The present invention relates to semiconductor processing and, more particularly, to CMOS processes including Lowly Doped Drain (LDD) region transistors.
2. Description of the Related Technology
With the continuous downscaling of MOSFET devices (Metal-Oxide-Semiconductor Field Effect Transistors) in the submicrometer region, the trade-off between the electrical performance of the devices and the reliability of the devices becomes a major issue. The performance of MOSFET devices is characterized by parameters such as drive current and speed. Drive current is defined as the current per micrometer width for an NMOS and PMOS transistor with maximum allowed voltages (=supply voltage for a given gate length technology) on gate and drain for the minimum allowed gate length in that specific technology. Speed is the maximum operational frequency as measured by the delay of an invertor ring oscillator at the supply voltage. The reliability of the device is determined by failure mechanisms such as dielectric breakdown, hot carrier degradation, electromigration, contact electromigration, stress migration, electrostatic discharge phenomena, latch-up, soft errors, radiation effects, corrosion, stability of interfaces, charge spreading, and mechanical stress. To overcome reliability problems arising from hot carrier effects in MOSFET devices with submicrometer gate lengths, adaptations in the fabrication process of the devices should be implemented. These adaptations in the processing sequence will lead to new device structures. A conventional approach is to implant a lowly doped region adjacent to the drain and source regions before spacer definition. Such devices are known as Lowly Doped Drain region devices (LDD devices).
Despite the fact that the supply voltage has been reduced from 5 V to 3.3 V and even to 2.5 V when scaling down the channel length of LDD MOSFET's below 0.6 .mu.m, hot-carrier degradation still remains a stringent limitation to the reliability of deep-submicron devices. To reduce the lateral electric field in NMOS LDD devices the concentration of the n-region between the channel and the n.sup.+ -junction should be lowered. Unfortunately this decrease in n.sup.- -concentration results in a higher series resistance R.sub.s, less current driveability, and an enhanced sensitivity of the device to the build-up of negative charge in the spacers during operation. This negative charge build-up causes an additional series resistance increase that leads to a severe drive current degradation. Therefore, in the optimization of conventional LDD transistors there exits a trade-off between the electrical performance on the one hand and the hot-carrier reliability on the other. To overcome this limitation various alternative device structures have been proposed in the past, such as LATID, inverse-T and GOLD in which the gate overlaps the n.sup.- -region to minimize the series resistance and its increase during degradation, R. Izawa, et al., "Impact of the Gate-Drain Overlapped Device (GOLD) for Deep Submicrometer VLSI", IEEE Trans on Electr. Dev. vol. ED-35, p. 2088, 1988; T. Hori, et al., "Deep-Submicrometer Large-Angel-Tilt Implanted Drain (LATID) Technology", IEEE Trans on Electr. Dev. vol. ED-39, p. 2312, 1992; T. Y. Huang, et al., "A Novel Submicron LDD Transistor with Inverse-T Gate Structure", IEDM Techn. Dig., p. 642, 1986. However, for these devices complex processing is required and the transistors can suffer from channelling or shadowing effects.